Method and apparatus for emulating an electrically erasable programmable read only memory (EEPROM) using non-volatile floating gate memory cells

ABSTRACT

An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array. The page row drivers and page source drivers are decoded by a page row/source supply decoder, based on the addresses to be accessed and the access mode (erase, program or read).

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. patentapplication Ser. No. 10/022,314, entitled “Electronically-ErasableProgrammable Read-Only Memory Having Reduced-Page-Size Program andErase,” filed Dec. 18, 2001, which is a continuation of U.S. patentapplication Ser. No. 09/564,324, entitled “Electronically-ErasableProgrammable Read-Only Memory Having Reduced-Page-Size Program andErase,” filed May 3, 2000, now U.S. Pat. No. 6,400,603, each assigned tothe assignee of the present invention and incorporated by referenceherein.

FIELD OF THE INVENTION

[0002] The present invention relates generally to a method and apparatusfor storing program code and/or data in a semiconductor circuit, such asa secure integrated circuit or a smart card, and more particularly, to amethod and apparatus for emulating an electrically erasable programmableROM (EEPROM) storage device using Flash cells.

BACKGROUND OF THE INVENTION

[0003] Semiconductor circuits generally include different memorytechnologies for storing program code and data. Typically, read onlymemory (ROM) storage technologies have been employed to store programcode and electrically erasable programmable ROM (EEPROM) storagetechnologies have been employed to store data. In order to reduce therequired surface area and the overall complexity of semiconductorcircuits, however, it is desirable to replace the ROM and EEPROM storagetechnologies with a single storage technology that is suitable forstoring both program code and data.

[0004] Over time, the meaning of the term “EEPROM” has changed from thegeneral meaning—electrically erasable programmable ROM—to a meaning thatrefers to a specific type of non-volatile memory. The specific type ofmemory is addressable in small, often byte-sized, segments and consistsof cells that generally contain two transistors. One transistor has afloating gate to store data; the second transistor is for selectionpurposes and isolates the floating gate transistor from the rest of thememory and therefore isolates unrelated electrical stimuli that canalter or “disturb” the data contents on the floating gate. The term“Flash” memory refers to memory architectures in which large numbers ofmemory cells are simultaneously written to the same data state—in a“flash.” Strictly speaking, Flash memories may consist of cells thatcontain any number of transistors, but the more recent, popular meaningrefers to cells that contain a single transistor. In the followingdescription, “EEPROM” refers to byte-addressable memories consisting oftwo-transistor memory cells and “Flash” refers to memories consisting ofsingle transistors, large numbers of which can be erased simultaneously.

[0005] Non-volatile floating gate memory cells, such as the split gateFlash cell from Silicon Storage Technology, Inc. (SSTI) of Sunnyvale,Calif., are attractive candidates for replacing both ROM and EEPROM, dueto their small cell size, high reliability, low power requirements, fasterase, and built-in select transistor. While EEPROM storage technologiesrequire two transistors for each memory cell, Flash storage technologiesonly require one transistor for each memory cell. Flash storagetechnologies can emulate ROM storage technologies quite easily.Emulating the ability of EEPROM storage technologies to rewrite smallportions of the memory array, however, proves quite difficult, mainlydue to disturb conditions and reduced endurance.

[0006]FIG. 1 illustrates a conventional array 100 of split gate Flashtransistors, such as the transistor MN0. Each split gate transistor isin a programmed or charged to a high threshold state when electrons aretrapped on the floating gate. The programmed state is reached byapplying a high voltage, on the order of 10 volts, to the source line(SOURCE) of the transistor MN0, a select voltage, on the order of 1.5volts, to the control gate (GATE) of the transistor MN0, and a constantcurrent, on the order of 2 μA, to the drain line (often referred to asthe bit line) (DRAIN) of the transistor MN0. Under the conditions of theprogrammed state, hot electrons are generated under the split gateregion and swept onto the floating gate by the high field that has beencoupled onto the floating gate. This programming condition is oftenreferred to as “source side channel hot electron programming.”

[0007] The selected transistor in an array 100 of transistors is thetransistor where the selected column intersects with the selected rowline. As shown in FIG. 1, there are several unselected transistors thatare subjected to one or more of the programming conditions but are notthe target (selected) cell. These cells are subject to program disturb,in which the electrical stimuli that are applied to the selectedtransistor are also partly, and undesirably, applied to the unselectedcells. If transistor MN0 is the target cell, transistor MN1 is subjectedto program conditions on the source and drain but has an unselected rowor gate. Transistor MN3 sees the program conditions on the row andsource lines but has an unselected drain line. The unselected conditionon any one of the three transistor nodes is enough to inhibitsignificant programming during a single cycle but some incrementalamount of disturb is incurred during each programming cycle. A largenumber of program cycles and therefore a large number of disturb eventsmay eventually lead to a memory failure.

[0008] The erased (low threshold) state of a split gate Flashtransistor, such as the transistor MN0, is achieved by discharging thefloating gate via tunneling. This is achieved by applying a high voltageto the row of the target cell, while the source and drain are grounded.Strong capacitive coupling between the floating gate and the source nodemaintains a low voltage on the floating gate. This produces a largeelectric field between the control gate and the floating gate andsubsequently electron tunneling, from floating gate to control gate, cantake place. If transistor MN0 is the target cell, transistor MN3 willalso be erased, since it shares a common row and source.

[0009] The architecture shown in FIG. 1 has a single source lineconnecting multiple pairs of rows. Alternatively, other prior artarchitectures have a single source line connecting a single pair ofrows. In this case, similar program disturb conditions exist to thosedescribed above, but the number of disturb events on any row can bereduced. The cells on one pair of rows are not exposed to a disturbvoltage on the source line during the time that a different pair of rowsis being programmed. Further improvements to disturb characteristics areobtained by performing an erase and programming all cells in the pair ofrows, as described, for example, in U.S. Pat. No. 5,289,411).Nevertheless, a large number of cells (i.e., much greater than a singlebyte) share a source line and a significant number of disturb events canoccur.

[0010] In addition to program disturb, prior art memory arrays utilizingFlash memory cells may have reduced effective endurance. In manyapplications, including smart cards, the number of bytes of new data tobe written at any one time is small. Since the erase block in a Flasharray is relatively large, many bytes in the same block do not need tochange data but are nevertheless erased because all bytes contained inthe same erase block must be erased simultaneously. Such bytes are firstread then erased and re-written with the same data that was heldpreviously. Thus, many bytes experience unnecessary erase andprogramming cycles that would not otherwise be required, if the eraseblock was small. The number of times that a single bit can be erased andprogrammed and still maintain its ability to store new data withouterrors is finite and is referred to as endurance. While the intrinsicendurance is a function of cell characteristics and is not appreciablyaffected by architecture, the unnecessary erase program cycles subtractfrom the total number of cycles available for useful data changes.

[0011] Furthermore, the relatively large size of the erase blockincreases the amount of time required to program new data, if the numberof bytes that are actually changing is small. Since all bytes containedin the same erase block must be erased simultaneously, there may bebytes that do not change but need to be re-written. Unlike the eraseoperation, the number of bytes that can be programmed simultaneously islimited by the capability of circuits peripheral to the memory array.Since the number of bytes that are programmed simultaneously is limited,the large erase block increases the required time to program smallamounts of data.

[0012] Many semiconductor circuits require the switching of highvoltages. For example, non-volatile memory devices on such semiconductorcircuits require voltages to erase and program the memory device thatare significantly higher than the voltages needed for other devicefunctions. For example, in one exemplary technology, voltages of 15volts on the gate and 10 volts on the source are required for the eraseand program modes, respectively. Gated diode breakdown is a well-knowncondition that can occur in a metal oxide semiconductor (MOS) transistorunder certain conditions. The drain/source breakdown voltage (BVDSS) isthe drain/source breakdown voltage with 0 volts applied to the gate ofan n-channel transistor and depends on the transistor fabricationprocess. In one exemplary technology discussed herein, BVDSS isapproximately 13 volts for both n-channel and p-channel transistors.Thus, to avoid gated diode breakdown, the voltage across thedrain/source must remain below the breakdown voltage, BVDSS, if the gatevoltage is grounded. As previously indicated, however, in manysemiconductor circuits, voltages greater than the breakdown voltage areneeded. For example, the erase and program operations for non-volatilememories on a secure integrated circuit require voltage levels of 15 and10 volts, respectively, on the high voltage power supply, V_(ep). Thus,the 15 volts required on the gate of an exemplary non-volatile memorydevice during an erase mode is generally higher than the BVDSS of thehigh voltage transistors.

[0013] A number of techniques have been proposed for avoiding gateddiode breakdown, such as placing an additional transistor in series withthe existing transistor. The additional transistor is typically gated byV_(dd), thus preventing the high voltage on the output from reaching thedrain of the existing transistor and limiting the drain voltage on theexisting transistor to a value below the breakdown voltage. While suchtechniques effectively prevent gated diode breakdown in the transistor,circuits including such gated diode breakdown protection techniques aretypically only capable of switching between an output voltage of 0 voltsand the high voltage level of 15 or 10 volts. For some applications,however, it is necessary, to switch between an output voltage of V_(dd)and the high voltage level of 15 or 10 volts, which is not possible withsuch cascoded transistor implementations. For a more detailed discussionof such gated diode breakdown protection techniques, see, for example,U.S. patent application Ser. No. ______, entitled “Method and Apparatusfor Avoiding Gated Diode Breakdown in Transistor Circuits,” (AttorneyDocket Number ATM-627) filed Jan. 8, 2003, assigned to the assignee ofthe present invention and incorporated by reference herein.

[0014] A need exists for an architecture and design that employnon-volatile floating gate Flash memory cells to emulate EEPROMfunctionality without incurring the program disturb issues discussedabove. A further need exists for an architecture that minimizes memoryoverhead by dividing a memory array into small pages. Another furtherneed exists for an architecture that reduces the number of unnecessaryerase/program cycles and improves both effective endurance and effectiveprogram speed when only small amounts of data are changing. Yet anotherneed exists for a protection circuit that prevents gated diode breakdownin N-channel transistors that have a high voltage across thedrain/source of the transistor, and provides greater flexibility on theoutput voltages that may be obtained.

SUMMARY OF THE INVENTION

[0015] Generally, an emulated EEPROM memory array is disclosed based onnonvolatile floating gate memory cells, such as Flash cells. Theemulated EEPROM memory array employs a common source line and common rowlines for a small group of bits, so that the small group of bits may betreated as an isolated group during program and erase modes. In thismanner, the issues of program disturb are controlled and, when data in asmall number of bytes is changing, program speed and effective enduranceis improved. The bits common to the shared source line make up theemulated EEPROM page, which is the smallest unit that can be erased andreprogrammed any number of times, without disturbing bits in other partsof the array. During an erase mode, the transistors connected to thesame source line, must be selected together. During a program or readmode, only the transistors connected to the common row and source lineswill see stress voltage. Thus, when a single byte is programmed, onlythe bytes sharing the same source line are subject to program disturb.These same bytes comprising an emulated EEPROM page in the architectureare erased as a group, thus the amount of disturb they receive islimited and predictable. Furthermore, since the page size is reduced,the time required to program all bytes in the page and the number ofunnecessary erase and program cycles can be reduced.

[0016] According to another aspect of the invention, the memory array isphysically divided up into groups of columns, to further reduce the sizeof an emulated EEPROM page. In one exemplary embodiment, there are fourmemory arrays, each consisting of 32 columns and 512 page rows (all fourarrays providing a total of 1024 pages with each page having 8 bytes or64 bits). In a memory sub-array consisting of single source lines, thenumber of columns in a sub-array directly affects the page size. On theother hand, the number of rows and total number of memory sub-arraysonly affect the total number of pages available in the emulated EEPROMmemory array. It is noted that a larger page size can be obtained byadding additional columns to each page, or by joining additional sourcesto the common source line. Likewise, a smaller page size, down to asingle byte, can be achieved by reducing the number of columns includedin each page or by reducing the number of bits attached to the commonsource.

[0017] A global row decoder is disclosed that decodes the major rows anda page row driver and a page source driver enable the individual rowsand sources that make up a given array. The page row drivers and pagesource drivers are decoded by a combination of the global row decoderand a page row/source supply decoder, based on the addresses to beaccessed and the access mode (erase, program or read). In this manner,the page row driver and page source driver contain minimum circuitry.The columns in a given array are decoded by a column decoder andmultiplexer. Once a given page row driver is selected by the global rowdecoder, the corresponding row line is activated across each of thememory arrays in the emulated EEPROM memory array. The global rowdecoder coupled with the supply decoders significantly reduce the sizeof the row/source driver logic in each memory array and is an importantaspect of the area efficiency and flexibility provided by thearchitecture of the present invention.

[0018] Protection circuits are also disclosed that prevent gated diodebreakdown in N-channel transistors that have a high voltage across thedrain/source of the transistor, and provide greater flexibility on theoutput voltages that may be obtained. The disclosed protection circuitscan be employed in the page row and page source driver circuits andstill provide desired output voltages. For example, the disclosed pagerow driver can deliver 0V, 1.5, VDD or 15V, as needed for various modesfor the non-volatile memory. In addition, in order to satisfy the needfor a more compact physical layout, the p-channel transistors in thepage row drivers and page source drivers share the same well. The wellsin adjacent page row drivers and page source drivers may also be joinedtogether.

[0019] A more complete understanding of the present invention, as wellas further features and advantages of the present invention, will beobtained by reference to the following detailed description anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a circuit diagram illustrating a conventional array ofsplit gate Flash transistors;

[0021]FIG. 2 is a schematic block diagram of an emulated EEPROM memoryarray incorporating features of the present invention;

[0022]FIG. 3 is a circuit diagram illustrating an exemplary embodimentof one of the memory arrays of FIG. 2 in further detail;

[0023]FIG. 4 is a schematic block diagram of the global row decoder ofFIG. 2;

[0024]FIG. 5 is a schematic block diagram of the page row/source supplydecoder of FIG. 2;

[0025]FIG. 6 is a schematic block diagram of the sets of page rowdrivers of FIG. 2;

[0026]FIG. 7 is a schematic block diagram of the sets of page sourcedrivers of FIG. 2;

[0027]FIG. 8 is a schematic diagram of a single page row driver within aset of eight page row drivers in the exemplary embodiment of FIG. 6; and

[0028]FIG. 9 is a schematic diagram of a single page source driverwithin a set of four page source drivers in the exemplary embodiment ofFIG. 7.

DETAILED DESCRIPTION

[0029] The present invention allows a smaller area of memory,corresponding to the emulated EEPROM page, to be erased at a time andreprogrammed, without disturbing other areas of the larger memory array.It is noted that a conventional Flash memory array programs one byte ata time, based on the selected page source, row and column. Assuming thata single source line is shared by eight rows in a conventional Flashmemory array having 128 columns, indicates that 127 bytes are disturbedwhen a single byte is programmed (8 rows times 128 bits, minus the bytebeing programmed). An emulated EEPROM memory array of similar size, inaccordance with the exemplary embodiment of the present invention,however, only disturbs eight bytes when a single byte is programmed.While Flash cells were generally intended to be used for applicationswhere large memory areas are erased or rewritten at a time (i.e., anentire memory array is typically erased at once), the present inventionallows Flash cells to be implemented in applications where smaller areasof a larger memory array are processed at a time.

[0030] It is noted that the term “page row/source supply decoder” usedherein corresponds to the terms “word lines” and “source lines” used inthe parent application, now U.S. Pat. No. 6,400,603 (hereinafter,referred to as the “'603 patent”). In addition, the terms “page rowdriver” and “page source driver” used herein correspond to the term“control” in the '603 patent, and the term “global row decoder” usedherein corresponds to the term “rowline” in the '603 patent.

[0031]FIG. 2 is a schematic block diagram of an emulated EEPROM memoryarray 200 incorporating features of the present invention. As shown inFIG. 2, the emulated EEPROM memory array 200 includes a plurality ofmemory arrays 300-1 through 300-N, discussed further below inconjunction with FIG. 3, embodied as Flash memory arrays. An exemplaryembodiment of the present invention physically divides the memory upinto four groups of X columns, where X is equal to the page size (inbytes) multiplied by eight divided by two. Thus, in an exemplaryembodiment, there are four memory arrays 300-1 through 300-4, eachconsisting of 32 columns (X equals 32) and 512 page rows. While thenumber of columns in a memory sub-array (300) consisting of singlesource lines directly affects the page size, the number of rows andtotal number of memory arrays only affect the total number of pagesavailable in the emulated EEPROM memory array 200, as would be apparentto a person of ordinary skill in the art. The exemplary embodiment,having four memory arrays 300-1 through 300-4, each consisting of 32columns and 512 page rows, provides 1024 pages with each page having 8bytes or 64 bits.

[0032] A global row decoder 400, discussed further below in conjunctionwith FIG. 4, decodes major rows in the emulated EEPROM memory array 200.The global row decoder 400 drives across each of the memory arrays 300-1through 300-N and enables sets of page row drivers 600 and page sourcedrivers 700, discussed further below in conjunction with FIGS. 6 and 7,respectively. The page row drivers 600 and page source drivers 700 areadditionally enabled by a page row/source supply decoder 500, discussedfurther below in conjunction with FIG. 5. Generally, the global rowdecoder 400 decodes the major rows and the page row drivers 600 and pagesource drivers 700 enable the individual rows and sources that make up agiven array 300. The columns in a given array 300 are decoded by acolumn decoder 250 and a column multiplexer 260.

[0033]FIG. 3 is a circuit diagram illustrating an exemplary embodimentof one of the memory arrays 300 of FIG. 2 in further detail. As shown inFIG. 3, each page consists of two rows, one source and 32 columns (bitlines). The bits on two adjacent rows share a common source line andtherefore are part of the same page. For example, the transistors MN0,MN1, MN3, MN4, MN14 and MN15 in FIG. 3 are connected to the same sourceline, pagesource0. According to one aspect of the invention, each of thepage rows connected to a common source are selected during an eraseoperation. Thus, the transistors connected to the same source linerepresent the smallest unit in the architecture of the present inventionand are treated as a group during an erase mode. During an erase mode,the transistors connected to the same source line, for example, thetransistors connected to pagerow0 and pagerow1 on page0 of FIG. 3, mustbe selected together. During a program or read mode, however, thetransistors connected to the same row line, such as pagerow0 on page0 ofFIG. 3 will experience approximately the same voltage on the source andpagerow lines, but appropriate voltages applied to the column lines canbe used to inhibit the bits that do not correspond to the target byte.In this manner, when a single byte is programmed, only the eight bytessharing the same source line are subject to program disturb. These sameeight bytes comprising a page in the architecture are erased as a group.Also in this manner, only the eight bytes sharing the same source lineare erased and programmed, thus reducing the time required to write newdata into the page, compared to the prior art, and also improving theeffective endurance when small numbers of bytes are written.

[0034] It is noted that a larger page size can be obtained by addingadditional columns to each page, or joining additional sources to thecommon source line. Likewise, a smaller page size can be achieved byreducing the number of columns included in each page.

[0035]FIG. 4 is a schematic block diagram of the global row decoder 400of FIG. 2. As shown in FIG. 4, the global row decoder 400 includes a rowdecoder 410-1 through 410-R for each global row in a given array 300.Thus, in the exemplary embodiment, the global row decoder 400 includes64 row decoders 410. A given row decoder 410 is selected based on anappropriate value on three input lines Ua, Ub and Uc, which can eachhave one of four possible values (4{circumflex over ( )}3 equals 64).Once a given row decoder 410 is selected, the corresponding row line isactivated across each of the memory arrays 300 in the emulated EEPROMmemory array 200.

[0036] As discussed further below in conjunction with FIGS. 6 and 7, foreach memory array 300, the selected row decoder 410 enables acorresponding global row signal, row[63:0], that is applied to one setof eight row drivers 610 and one set of four source drivers 710. It isnoted that the global row decoder 400 enabling each of the memory arrays300 in the emulated EEPROM memory array 200 significantly reduces thesize of the row/source driver logic (600, 700) corresponding to eachmemory array 300 and is an important aspect of the area efficiencyprovided by the architecture of the present invention. In a furthervariation, the decoding could be repeated in each memory array, andalthough feasible, would be expensive in terms of area.

[0037]FIG. 5 is a schematic block diagram of the page row/source supplydecoder 500. As shown in FIG. 5, the page row/source supply decoder 500includes a front end pre-decoder 510 that receives one or moreaddresses, and control inputs to indicate whether the contents of theaddressed byte(s) are to be read, programmed or erased. Based on theindicated address(es) and access mode, for a program or read mode, thepre-decoder 510 in conjunction with the logic plus level converters 520in the page row/source supply decoders 500 will select one of 32 rowpages (via signal “rowsupply[n])”and one of 16 source pages (via signal“sourcesupply[n]”). For an erase mode, the pre-decoder 510 inconjunction with the logic plus level converters 520 in the pagerow/source supply decoders 500 will select two of 32 row pages and oneof 16 source pages corresponding to the indicated addresses. Note that apair of rows are selected during an erase mode because the exemplaryembodiment includes a page size of two rows and one source. It is alsonoted that the page row/source supply decoder 500 decodes the suppliesto the page row and page source drivers 600, 700. By decoding thesupplies in this manner, no additional decoding circuitry is needed inthe drivers 600, 700 when combining the outputs from the global rowdecoder 400. The drivers themselves act as decoders. The combination ofdecoding global rows and pagerow/pagesource supplies in this mannerfurther increases the efficiency of the architecture of the presentinvention.

[0038] The output of the pre-decoder 510, selectrow, is a 32 bit valueindicating the selected row page(s) (and implicitly, the correspondingsource page). The selectrow value is applied to a set of logic and levelconverter buffers 520-1 through 520-N. In the exemplary embodiment, theemulated EEPROM memory array 200 is divided into four memory arrays 300and there is a logic and buffer 520 corresponding to each memory array300. The selectrow value is translated by the appropriate logic andbuffer 520 to activate the appropriate rowsupply and sourcesupply outputsignals. The rowsupply and sourcesupply outputs of each logic and buffer520 are applied to the corresponding inputs of the page row drivers 600and page source drivers 700 of the associated memory array 300.

[0039]FIG. 6 is a schematic block diagram of the sets of page rowdrivers 600 of FIG. 2. As shown in FIG. 6, the exemplary embodimentincludes 256 sets of page row drivers 610-1 through 610-K. Each set ofpage row drivers drives eight page rows. The first vertical column of 64page row drivers 610-1 through 610-64 is associated with the firstmemory array 300. For example, the first set of 64 page row drivers610-1 through 610-64 is activated by the rowsupply output of the firstlogic and level converter buffer 520-1 of FIG. 5. The rowsupply output,together with the active global row line, row0 through row63, determineswhich single page row driver within a set of page row drivers 610 isactivated. It is again noted that, in an erase mode, two adjacent rowsare selected, while, in a program or read mode, only one row isselected.

[0040]FIG. 7 is a schematic block diagram of the sets of page sourcedrivers 700 of FIG. 2. As shown in FIG. 7, the exemplary embodimentincludes 256 sets of page source drivers 710-1 through 710-K. Each setof page source drivers drives four page sources. The first verticalcolumn of 64 page source drivers 710-1 through 710-64 are associatedwith the first memory array 300. For example, the first set of 64 pagesource drivers 710-1 through 710-64 is activated by the sourcesupplyoutput of the first ogic and level converter buffer 520-1 of FIG. 5. Thesourcesupply output, together with the active global row line, row0through row63, determines which single page source driver within a setof page source drivers 710 is activated. It is again noted that a singlepage source is selected in an erase, program or read mode.

Breakdown Protection

[0041] As previously indicated, certain voltages need to be applied tocells within the memory array 300 to perform read, erase and programoperations. By way of example, FIG. 1 and FIG. 3 show arrays of splitgate Flash cells, which may be embodied, for example, using the splitgate Flash cells from Silicon Storage Technology, Inc. (SSTI) ofSunnyvale, Calif. The operation and voltage requirements of such cellsare described in U.S. Pat. No. 6,400,603, incorporated herein byreference. While certain other types of cells may be substitutedinstead, the SSTI cell is used to illustrate the present invention.Table 1 shows the voltages required to perform read, erase and programoperations for the exemplary SSTI cells. High voltages such as 15V onthe row and 10V and on the source are required for erase and program,respectively. A high voltage of 15V is used because it results indesirable erase characteristics such as reduced erase time, lower erasethreshold and/or improved erase distribution statistics.

[0042] Read TABLE 1A Read Voltages Unselected Selected row, Selectedrow, Unselected Row, selected unselected Row, selected unselected columncolumn column column Row VDD (2.5V) VDD (2.5V) 0V 0V Source 0V 0V 0V 0VColumn ˜1.5V 0C/float ˜1.5V 0V/float

[0043] Erase tABLE 1B Erase Voltages Unselected Selected row, Selectedrow, Unselected Row, selected unselected Row, selected unselected columncolumn column column row 15V 15V 0V 0V source  0V  0V 0V 0V column  0V 0V 0V 0V

[0044] Program TABLE 1C Program Coltages Unselected Selected row,Selected row, Unselected Row, selected unselected Row, selectedunselected column column column column row 1.5V 1.5V 0V 0V source  10V 10V 0V 0V column ˜2 μA   0V ˜2 μA 0V

[0045] The voltages shown in Table 1 are coupled onto the pagerow andpagesource nodes of FIG. 3 by the page row drivers 600 and page sourcedrivers 700. The drivers need to couple high voltages onto selectedpagerows and pagesources and also isolate high voltages from unselectedpagerows and pagesources. A circuit that utilizes a single passtransistor and single discharge transistor, such as the circuitdescribed in FIG. 4A of U.S. Pat. No. 6,400,603, is unsuitable for thepresent application. A voltage of 15V, as supplied to the input of apage row driver 600 is higher than the BVDSS of the high voltagetransistors. As indicated above, BVDSS is the drain/source breakdownvoltage with 0V applied to the gate of an n-channel transistor. For theexemplary technology discussed herein, BVDSS is approximately 13 voltsfor both n-channel and p-channel transistors. Therefore, if a singlen-channel transistor is used to isolate an unselected pagerow byapplying 0V to the gate of the single transistor, the BVDSS breakdownwould limit the voltage on the high voltage supply and the voltagecoupled to the selected pagerow would be reduced, as is well known. Notethat high voltage supplies, as typically used on non-volatile memorieshave a high internal resistance and have a limited current sourcingcapability. In any case, breakdown is undesirable and should be avoided.

[0046] Thus, a circuit is required to couple and isolate high voltagesonto the pagerow and pagesource, as listed in Table 1. In the case ofthe pagerow, the voltage is above BVDSS. The required circuit is closelycoupled to the memory arrays 300 and is repeated multiple times andphysically located adjacent to the memory array 300. Thus, the requiredcircuit should be physically compact so as to facilitate physical layoutand interface to the small dimensions of a memory page.

[0047]FIG. 8 is a schematic diagram of a single page row driver 800. Theoutput “page_row” corresponds to any one of the signals pagerow [2047:0]of FIG. 6. The global row signals, row[63:0], that are generated by theglobal row decoder 400 shown in FIG. 4 are comprised of the“global_row_low,” “global_row_high_b”, and “global_row_low_b” signalsthat are applied as inputs to the single page row driver 800 of FIG. 8.“Vep” is a voltage supply, the level of which is dependent on theoperating mode (erase, program or read) that is active. Similarly, thesignals rowsupply[31:0] in FIGS. 5 and 6 are comprised of the “page_rowsupply_low” and “page_row_supply_high” signals that are applied asinputs to the single page row driver 800 of FIG. 8.

[0048]FIG. 9 is a schematic diagram of a single page source driver 900.The output “page_source” corresponds to any one of the signalspagesource [1023:0] of FIG. 7. The global row signals, row[63:0], thatare generated by the global row decoder 400 shown in FIG. 4 arecomprised of the “global_row_low,” “global_row_high_b”, and“global_row_low_b” signals that are applied as inputs to the single pagesource driver 900 of FIG. 9. “Vep” is a voltage supply, the level ofwhich is dependent on the operating mode (erase, program or read) thatis presently active. Similarly, the signals rowsupply[31:0] in FIGS. 5and 6 are comprised of the “page_source_supply_low” and“page_source_supply_high” signals that are applied as inputs to thesingle page source driver 900 of FIG. 9.

[0049] The voltages that are applied to the input signals of FIGS. 8 and9 are shown in Table 2.

[0050] Read TABLE 2A Voltages applied to Page Row and Source Sriversduring READ un- selected elected selected global un-selected globalglobal row/un- global row/un- row/selected selected row/selectedselected Signals supply supply supply supply Vep Vdd(2.5) Vdd(2.5)Vdd(2.5) Vdd(2.5) page_row_supply_low Vdd(2.5) 0V Vdd(2.5) 0Vpage_row_supply_high Vdd(2.5) 0V Vdd(2.5) 0V page_source_supply_low 0V0V 0V 0V page_source_supply_high 0V 0V 0V 0V global_row_high_b 0V 0VVdd(2.5) Vdd(2.5) global_row_loow_b 0V 0V Vdd(2.5) Vdd(2.5)global_row_low Vdd(2.5) 0V 0V 0V page_source 0V 0V 0V 0V

[0051] Erase TABLE 2B Voltages applied to Page Row and Source Driversduring ERASE un- selected elected selected global un-selected globalglobal row/un- global row/un- row/selected selected row/selectedselected Signals supply supply supply supply vep 15V 15V 15V 15Vpage_row_supply_low Vdd(2.5)  0V Vdd(2.5)  0V page_row_supply_high 15VVdd(2.5) 15V Vdd(2.5) page_source_supply_low  0V  0V  0V  0Vpage_source_supply_high Vdd(2.5) Vdd(2.5) Vdd(2.5) Vdd(2.5)page_row_high_b Vdd(2.5) Vdd(2.5) 15V 15V global_row_low_b  0V  0VVdd(2.5) Vdd(2.5) global_row_low Vdd(2.5) Vdd(2.5)  0V  0V page_row 15V 0V  0V  0V page_source  0V  0V  0V  0V

[0052] Program TABLE 2C Voltages applied to Page Row and Source Driversduring PROGRAM un- selected selected selected global un-selected globalglobal row/un- global row/un- row/selected selected row/selectedselected Signals supply supply supply supply vep 10V 10V 10V 10Vpage_row_supply_low  1.5V  0V  1.5V  0V page_row_supply_high  1.5V  0V 1.5V  0V page_source_supply_low Vdd(2.5)  0V Vdd(2.5)  0Vpage_source_supply_high 10V  0V 10V  0V global_row_high_b  0V  0V 10V10V global_row_low_b  0V  0V Vdd(2.5) Vdd(2.5) global_row_low Vdd(2.5)Vdd(2.5)  0V  0V page_row  1.5V  0V  0V  0V page_source 10V  0V  0V  0V

[0053] Table 2 shows that the possible output voltages on page_row are0V, 1.5V, VDD (2.5V) and 15V. High voltage p-channel transistors arerequired to transfer 15V without voltage loss. An n-channel transistorwould not be suitable for this purpose due to the prohibitively largevoltages that would be required on the gate, resulting in breakdown andreliability problems. Thus, referring to FIG. 8, transistors MP2 and MP3provide the path that connects page_row to page_row_supply_high. Notethat in order to satisfy the need for compact physical layout, allp-channel transistors in the page row driver 800 and all p-channeltransistors in the page source driver 900 must share the same well. Thewells in adjacent page row drivers 800 and page source drivers 900 mayalso be joined together. A well is connected to the highest voltagesupply, which is Vep, and can result in considerable threshold increasesto the p-channel transistors. For example, in the exemplary embodiment,a back bias of 10V results in a high voltage p-channel transistorthreshold greater than 1.5V. Thus, n-channel transistor MX25, whichexperiences much lower back bias, provides a path to page_row_supply_low(1.5V during program) for the selected row. Transistors MX23 and MX24provide a path to Vss (0V) for the unselected row.

[0054] Transistors MX23 and MP2 act as high voltage cascode transistorsthat allow the circuit to avoid gated diode breakdown (i.e., operateabove BVDSS). An important aspect of the invention is the combination ofcontrol and supply voltages that, when operating in cooperation with thecascode transistors, avoids gated diode breakdown in all functionalmodes. The key is not switching the high voltage (HV) supplies(page_row_supply_high, page_source_supply_high) and (HV) control line(global_row_high_b) to groundwhen unselected during erase but insteadswitching them to V_(DD). For instance, during erase, VDD on the gate oftransistor MP2 increases the breakdown of the unselected row, and V_(DD)on the gate of transistor MP3 and V_(DD) on the unselected supplyincreases the breakdown of the selected row, unselected supply. The paththrough transistor MP3 for the selected global row/unselected supply isturned off by also reducing the page_row_supply_high from 15V to V_(DD).To avoid gated-diode breakdown during erase in selected globalrow/selected supply condition, both page_row_supply_low andglobal_row_low are brought to VDD.

[0055] Referring to FIG. 9, transistors MP5 and MP6 connect page_sourceto page_source_supply_high source (which could be at a voltage equal toV_(DD) or 10V). Transistors MP5 and MP6 are cascoded for gated-diodeprotection during erase, during which time the voltage on their well isequal to 15V. Therefore, to protect transistor MP5 against breakdown,the voltage on page source_supply_high is taken to V_(DD) during erase.Transistor MX28 provides a path to ground for unselected global rows.Transistor MX27 is needed to provide a path for the selected global rowsto apply 1.5V to page_rows during programming.

[0056] The details of the circuits employed in the global row decoder400 and the page row/source supply decoder 500 are not shown. Rather, itis the combination of control voltages and supply voltages (i.e., theoutput voltages of the global row decoder 400 and the page row/sourcesupply decoder 500), operating in cooperation with the circuits shown inFIGS. 8 and 9 that is pertinent to the present invention. Examples ofthe circuit design techniques that can be employed in the global rowdecoder 400 and the page row/source supply decode 500 are described inco-pending U.S. patent application Ser. No. ______, entitled “Method andApparatus for Avoiding Gated Diode Breakdown in Transistor Circuits,”(Attorney Docket Number ATM-627) filed Jan. 8, 2003, assigned to theassignee of the present invention and incorporated by reference herein.

[0057] While the memory architectures described herein have beendemonstrated, by way of example, with a split gate cell, it should benoted that various other memory cell types might also be employed.Moreover, the examples contained within are illustrative and severalvariations are possible within the context of the invention. The numberof cells within a page, the number of pages that are coupled to page rowdrivers and page source drivers and the number of pages within an arraycan be modified according to the requirements of the application.Endurance, average write time per cell, compactness, ease of interfacingand control are features that can be altered by adjusting the aboveparameters.

[0058] Increasing the number of cells within a page can reduce theaverage write time per cell because the single, more lengthy, eraseoperation is shared between more cells, albeit at the cost of a longerprogramming time. This is advantageous for systems in which large blocksof data are being written simultaneously and can also result in a morecompact physical layout. However, this is at the cost of reducedendurance for applications that change small amounts of data at any onetime and also at the cost of an increased number of disturb events. Anincreased number of pages per page row driver and page source driver andan increased number of cells per page can increase the physicaldimensions in the vertical and horizontal directions, respectively.Since the memory cell array consists of an array of single transistors,usually with minimum feature sizes, the additional physical space at theperiphery of the array is advantageous. Such space facilitates theplacement of global row decoders 400, page row/source supply circuits500, page row drivers 600 and page source drivers 700. Thus, thearchitecture can be modified in order to achieve the desired trade offbetween endurance, disturb, page write time, average write time percell, data organization, ease of interfacing and physical compactness.

[0059] It is to be understood that the embodiments and variations shownand described herein are merely illustrative of the principles of thisinvention and that various modifications may be implemented by thoseskilled in the art without departing from the scope and spirit of theinvention.

We claim:
 1. An array of non-volatile floating gate memory cellsarranged in a plurality of rows and columns, a plurality of said memorycells electrically coupled to form a plurality of pages, said arraycomprising: a plurality of page row lines, each of said page row linesconnected to a gate of one or more of said memory cells in one of saidrows; a plurality of page source lines, each of said page source linesconnected to a source of one or more of said memory cells in one of saidpages, wherein each of said pages includes each of said plurality ofnon-volatile floating gate memory cells that are subject to programdisturb when at least one of said plurality of non-volatile floatinggate memory cells is programmed; and a plurality of column lines, eachof said column lines connected to a drain of all of said memory cells inone of said columns.
 2. The array of claim 1, wherein said non-volatilefloating gate memory cells are flash cells.
 3. The array of claim 1,wherein each of said pages of memory cells sharing a common source lineincludes at least two rows of said memory cells in said array.
 4. Thearray of claim 1, wherein said columns in said array are further dividedinto a plurality of sub-arrays comprised of groups of columns to reducea size of said pages. Should claim how it is done. In this case, I thinkthe claim is too general. not sure what you meant here
 5. The array ofclaim 1, wherein said page rows lines associated with each of saidmemory cells in one of said pages must be selected during an eraseoperation.
 6. The array of claim 1, further comprising a global rowdecoder to decode major rows in said memory array.
 7. The array of claim6, further comprising a set of page row drivers that are decoded by saidglobal row decoder and a page row supply decoder, based on said memorycells to be accessed and an indication of an access mode to enableindividual rows of said array.
 8. The array of claim 6, furthercomprising a set of page source drivers that are decoded by said globalrow decoder and a page source supply decoder, based on said memory cellsto be accessed and an indication of an access mode to enable theindividual sources of said array.
 9. The array of claim 1, furthercomprising a decoder for decoding page rows and page sources in saidmemory array.
 10. A method for erasing a memory array comprised of aplurality of non-volatile floating gate memory cells arranged in aplurality of one or more rows and columns, each of said memory cellshaving a drain, gate and source terminal, a plurality of said memorycells electrically coupled to form a plurality of pages, said methodcomprising: applying a voltage to a plurality of page source linesconnected to a gate of each of said memory cells in one of said pages,wherein each of said pages includes each of said plurality ofnon-volatile floating gate memory cells that are subject to programdisturb when at least one of said plurality of non-volatile floatinggate memory cells is accessed.
 11. The method of claim 10, wherein saidnon-volatile floating gate memory cells are flash cells.
 12. The methodof claim 10, wherein each of said pages of memory cells sharing a commonsource line includes at least two rows of said memory cells in saidarray.
 13. The method of claim 10, wherein said columns in said arrayare further divided into a plurality of sub-arrays comprised of groupsof columns to reduce a size of said pages. Should claim how it is done.In this case, I think the claim is too general. not sure what you meanthere
 14. The method of claim 10, wherein said page rows lines associatedwith each of said memory cells in one of said pages must be selectedduring an erase operation.
 15. The method of claim 10, furthercomprising the step of decoding major rows in said memory array using aglobal row decoder.
 16. The method of claim 10, further comprising thestep of decoding page rows and page sources in said memory array.
 17. Amethod for avoiding gated diode breakdown in a row driver circuit for anonvolatile memory array, said row driver circuit having at least twoN-channel output driver transistors in series, said row driver circuitcapable of switching between a high voltage level and a lower railvoltage in a high voltage mode, said method comprising the steps of:providing a control signal to a gate of one of said at least twoN-channel output driver transistors to select between said high voltagelevel and said lower rail voltage; and selectively providing a highvoltage supply to a source of said one of said at least two N-channeloutput driver transistors, wherein said control signal and said highvoltage supply are switched to said lower rail voltage for an unselectedrow.
 18. The method of claim 17, wherein said at least two N-channeloutput driver transistors provide a path that connects said high voltagelevel to an output in an erase mode.
 19. The method of claim 17, whereinsaid at least two N-channel output driver transistors provide a paththat connects said lower rail voltage to an output in a read mode. 20.The method of claim 17, wherein a third N-channel output drivertransistor provides a path that connects a lower voltage level to anoutput in a read mode.
 21. The method of claim 17, wherein twoadditional N-channel transistors provide a path that connects ground toan output for an unselected row.
 22. The method of claim 17, whereineach of said at least two N-channel transistors share a common well. 23.The method of claim 22, wherein each of said at least two N-channeltransistors in adjacent row drivers share a common well.
 24. A rowdriver circuit for a non-volatile memory array capable of switchingbetween a high voltage level and a lower rail voltage in a high voltagemode, comprising: at least two N-channel output driver transistors inseries, wherein a control signal is applied to a gate of one of said atleast two N-channel output driver transistors to select between saidhigh voltage level and said lower rail voltage; and a high voltagesupply is selectively applied to a source of said one of said at leasttwo N-channel output driver transistors, wherein said control signal andsaid high voltage supply are switched to said lower rail voltage for anunselected row.
 25. A method for avoiding gated diode breakdown in asource driver circuit for a nonvolatile memory array, said source drivercircuit having at least two N-channel output driver transistors inseries, said source driver circuit capable of switching between a highvoltage level and ground, said method comprising the steps of: providinga control signal to a gate of one of said at least two N-channel outputdriver transistors to select between said high voltage level and saidlower rail voltage; and selectively providing a high voltage supply to asource of said one of said at least two N-channel output drivertransistors, wherein said control signal and said high voltage supplyare switched to said lower rail voltage for an unselected row.
 26. Themethod of claim 25, wherein each of said at least two N-channeltransistors share a common well.
 27. The method of claim 26, whereineach of said at least two N-channel transistors in adjacent sourcedrivers share a common well.